When variable width pulses are generated with voltage ramp generators and comparators, less than 100% of the voltage ramps may be utilized. This is due to the fact that the comparator must have some level of overdrive to assure a stable state. In some cases the input clock signal driving the voltage ramp is a 50% duty cycle signal; then the voltage ramp can be made to operate for 50% of the clock cycle. With two or more alternating ramps generated there is a ramp on at all times and an alternate ramp off at all times. See U.S. Pat. No. 5,317,199, issued May 31, 1994, "Ramp Generator System", by Edward Perry Jordan; U.S. Pat. No. 5,295,158, issued Mar. 15, 1994, "Dynamically Selectable Multimode Pulse Width Modulation System", by Edward Perry Jordan; and U.S. Pat. No. 5,283,515, issued Feb. 1, 1994, "Automatic Calibration System for a Ramp Voltage Generator", by Edward Perry Jordan. Using two ramps has the advantage of doubling the system speed. A digital to analog converter (DAC) can be compared against one ramp to generate a variable width output pulse. During the time one DAC and ramp are being used to generate one pulse, a new value can be loaded into the DAC associated with the off voltage ramp. Thus a series of variable width sequential pulses can be generated by alternating ramps. This approach has a problem in that two sequential full width pulses will not touch. Any pulse generated by a system such as this will not extend through the full ramp period (this is due to non ideal comparators). Two sequential full width pulses will have a gap between them.
In certain applications it is advantageous to use 100% of the ramp's period to generate pulses that extend up to 100% of the voltage ramp's period. This would require extremely fast and extremely high gain comparators to generate full width pulses. These approaches are expensive and impractical for higher volume low cost production.